Freeware Verilog?

Considering there are quite a lot of Verilog clones around (some quite cheap), why build another - and free too? Well, there are several reasons:
1. Most of the existing simulators are deficient in some area (capacity, performance or price).
2. None of them are designed for use in mixed-mode with analog simulators.
3. None use parallel processing effectively.
4. Any time someone wants to build a new EDA tool they have to write a whole lot of analysis and elaboration code (and debug it) that they (or other) people have already done many times.
5. Verilog has a large (global) user base, and hence significant potential for development support and testing from the user community.
6. There is a significant amount of useful reusable IP (Intellectual Property) described in Verilog, which needs a common support system.
7. Existing simulators have limited support for bug fixing/enhancement.
8. The time taken to build a new (complete) Verilog-AMS/VHDL system is longer than most EDA Companies or Venture Capitalists will support when there are already a few competitors and the market is saturated.

Why Verilog and not VHDL is dicussed below, and elsewhere.

Verilog is not VHDL

H.D.L. Can be interpreted two ways:

1. Hardware Design Language

   A language used to specify hardware.

2. Hardware Description Language

   A language used to describe actual hardware.

VHDL is quite good for the first of these but is not as good at the second because of it's simulation semantics and syntactic restrictions, and lack of primitive types. It's regularity, formality and ability to describe abstract data types allow easy specification of high-level concepts. It can be implemented fairly directly from the IEEE LRM (Language Reference Manual) with some knowledge of computer science and programming (and without a knowledge of electronics) - hence it's popularity with academics and people who don't actually build hardware.

Verilog as it's name implies is more directly targeted at verifying hardware implementation, i.e. it has hardwired primitives (gates and transistors) and the simulation algorithms/semantics are tuned for speed. Abstract data types are unnecessary for this task and therefore were not added to the language, however "probing" and "test-benching" are necessary, and so hierarchical references and PLI (Program Level Interface for user (C) code) were added. The IEEE LRM is not a sufficient document for implementing a Verilog simulator that would be customer-acceptable.

VHDL and Verilog are more complimentary than overlapping, the former is suited to top-down design and the latter to bottom-up implementation. There is already a freeware VHDL project underway which proposes to have a binary intermediate form. The intention of the V2000 project is to use the FreeHDL project's intermediate form at a later date to create a combined Verilog-VHDL simulation environment.

Analog HDLs

Two new HDLs have been introduced to enable users to describe analog behavior: Verilog-A and VHDL-A; the former based on Cadence's Spectre product and being the first step in the specification of Verilog-AMS, the latter being just an extension of VHDL.

VHDL-A is debilitated by pre-existing deficiencies in VHDL (as mentioned above). It is also probably less usable than Verilog-A because of the lack procedural constructs and poor debugability, also Verilog-A is a superset functionally.

Verilog-A suffers from similar LRM deficiences to Verilog in that it is a loose description of what Cadence actually implemented.

Neither language has official primitives, however most implementations are built on top of "Spice" simulators, and allow direct instantiation of the modules and primitives in the input deck (the input is usually a mix of "spice deck" and V* source).

Mixed Signal - Analog & Digital - Simulation

The two languages for this are (obviously) Verilog-AMS or VHDL, however due to the bad semantics of simulation and elaboration it is unlikely that as they stand they are really what the users want. Particularly since the Verilog-AMS standard is only just creeping its way to the IEEE for proper standardisation (where there will probably be a debate about whether they should bother since there is already a similar VHDL-A standard).

Aims of the V2000 Project

The aim of the V2000 project is to circumvent the politics of the EDA vendors and OVI/IEEE committees and implement a Verilog-AMS (and VHDL) simulator system without the bugs and semantic problems that those committees have failed to fix. This is not to say it should be incompatible with the standards, only that it should "do the right thing", much as the GNU project compiler gcc (and g++) is compatible with standard ANSI C code but has numerous useful features on top. Intended features of the project include:

• Extremely high capacity
• Parallel Processing in analysis and simulation.
• Support for Intellectual Property
• Splitting (seperating digital from analog, VHDL from Verilog after Elaboration for multi-simulator simulations).
• Better specification of simulator capabilities.
• Dynamic re-elaboration of sub-sections of hierarchy.
• Dynamic back-annotation for mixed-signal/analog simulation.

The schedule for implementation has the following phases:

1. Build the Verilog-AMS parser, intermediate form writer, and then the elaborator (working from the intermediate form).
2. Add hooks for "plug-ins". (Perl, C/C++).
3. An interpretive simulation kernel and then PLI, VPI, VCD and other interfaces (or integrate someone else's).
4. Just-in-time Verilog[-A] -> C++ generator/compiler/linker.¹
5. Integrate Spice 3 solver and models.
6. Integrate FreeHDL work.

It's worth noting here that although previous analyzer systems may have focused on creating an intermediate form for modules or package and entity-architecture data, most tools prefer to work on elaborated data, for which there is not really any standard support (other than through the PLI of some simulators). So phase 1 & 2 will produce a useful tool base for other projects e.g. rule-checkers and synthesis tools.

SystemVerilog adds some user friendly syntax which may be incorporated into the parser. The other components of SystemVerilog derived from C and Java (from Vera) are not really much of an improvement on the original languages. C++ is the language being used for code generation so it will be the natural language for future extensions, i.e. future extensions will be based on C++ syntax and semantics in preference to other languages. Java support may also be added for handling pre-compiled platform independent IP.

The aim of the V2000 project is to provide a vehicle for other EDA toolsand Intellectual Property, some of which will not be viable as freeware. For this reason it is distributed under the GNU 'Lesser General Public License', which allows it to be linked into code distributed under other licences.