VHDL vs. Verilog

If you feel that Verilog is "the best thing since sliced bread" and VHDL is the worst comittee effort ever (or vice versa) you can get a link here. My personal opinion is that Verilog is a better abstraction of actual hardware, and that in general when you model things in software, the greater the similarity in behavior of the software and the target system the better. VHDL models an abstraction rather than actual hardware and that is its failing, and conversely Verilog's lack of support for more abstract constructs is its failing. However just as C++ started out as a preprocessor to C, I feel that the future of HDLs is based in Verilog - though probably through the efforts of the freeware EDA community raher than the OVI or IEEE in the 3rd millenium.

Verilog vs. VHDL John Sanguinetti

INDUSTRY GADFLY: "From Beirut To Bosnia" + Reader Response John Cooley

Verilog Won & VHDL Lost -- You Be The Judge John Cooley

Verilog Compared & Contrasted Douglas J. Smith