System What?
Should you be using C++, SystemC or SystemVerilog? The answer does (of course)
depend on what your trying to do. If you are trying to write complex testbenches
for Verilog designs then maybe SystemVerilog is for you (it's a no-brainer if
you're already a Vera fan). If you are thinking of trying to do some software/hardware
trade-off in the early stages of a design then maybe C++/SystemC will work better
for you.
SystemVerilog (SV) currently does not support many features of C++, and although it may
be "safer" to program it is a different language with limited vendor support - you
won't find a compiler for your favorite embedded processor for the parts that
end up software rather than hardware. It has
no extensions which really address the problems of deep-sub-micron design, or
support new synthesis methodologies. It also has various syntax/semantic oddities
that make it difficult to do top-down design - i.e. SV modules (and interfaces) do
not decompose easily into synthesizable/realizable Verilog.
Joe Costello may have said "VHDL was a $400 million mistake" and Aart De Geus may agree, but
SV may also sink a lot of Synopsys's money before customers really get what they need.
The original objective of the V2000 project was to implemement a Verilog-AMS simulator
system, however since that plan was made in 1998 there has been relatively little
progress on the freeware analog simulator front and quite a lot of progress on system
level languages. The current plan is to add efficient bridges from V2000 into C++,
and to add extensions that fit easily into the parser/code-generator that make it easier
to do hardware/software trade-off and make C++ a better simulation environment.